#include <stm8s_tim1.h>

void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
{
  /* Check the parameters */
  assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
  assert_param(IS_TIM1_OCM_OK(TIM1_OCMode));
  
  if (TIM1_Channel == TIM1_CHANNEL_1)
  {
    /* Disable the Channel 1: Reset the CCE Bit */
    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
    
    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) 
                            | (uint8_t)TIM1_OCMode);
  }
  else if (TIM1_Channel == TIM1_CHANNEL_2)
  {
    /* Disable the Channel 2: Reset the CCE Bit */
    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
    
    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
                            | (uint8_t)TIM1_OCMode);
  }
  else if (TIM1_Channel == TIM1_CHANNEL_3)
  {
    /* Disable the Channel 3: Reset the CCE Bit */
    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
    
    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) 
                            | (uint8_t)TIM1_OCMode);
  }
  else
  {
    /* Disable the Channel 4: Reset the CCE Bit */
    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
    
    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) 
                            | (uint8_t)TIM1_OCMode);
  }
}

/**
  * @brief  Sets the TIM1 Counter Register value.
  * @param   Counter specifies the Counter register new value.
  * This parameter is between 0x0000 and 0xFFFF.
  * @retval None
  */
